Addisjonskrets for IEEE-754 flyttall : optimalisert for gjennomstrømning
dc.contributor | Gundersen, Rune | en_GB |
dc.contributor | Blom, Harald | en_GB |
dc.date.accessioned | 2018-10-29T12:21:41Z | |
dc.date.available | 2018-10-29T12:21:41Z | |
dc.date.issued | 2000 | |
dc.identifier | ||
dc.identifier.isbn | 82-464-0396-6 | en_GB |
dc.identifier.other | 2000/00138 | |
dc.identifier.uri | http://hdl.handle.net/20.500.12242/1773 | |
dc.description.abstract | This report conlains a description of a floating-point adder optimized for throughput rather than latecy. It is confirmed with lEEE-754 standard for binary floating-point arithmetic. The design is fully tested and verified. Synthesis results for the A1catel Mietec MTC45000 technology are presented. | en_GB |
dc.language.iso | nob | en_GB |
dc.title | Addisjonskrets for IEEE-754 flyttall : optimalisert for gjennomstrømning | en_GB |
dc.subject.keyword | Integrerte kretser | en_GB |
dc.source.issue | 2000/00138 | en_GB |
dc.source.pagenumber | 85 | en_GB |