Addisjonskrets for IEEE-754 flyttall : optimalisert for gjennomstrømning

Abstract

This report conlains a description of a floating-point adder optimized for throughput rather than latecy. It is confirmed with lEEE-754 standard for binary floating-point arithmetic. The design is fully tested and verified. Synthesis results for the A1catel Mietec MTC45000 technology are presented.